The present disclosure relates to a method and system of testing an integrated circuit (IC), using a method of compression with hardware support to limit aliasing of a multiple input shift register (MISR) for diagnosing failure locations in an IC with built-in self-test (BIST) logic, including On-Product multiple input shift register (OPMISR) logic.
Design for testing (DFT) includes IC design techniques that add testability features to a hardware product design. The added features make it easier to develop and apply manufacturing tests to the designed hardware. The purpose of manufacturing tests is to validate the product hardware as containing no manufacturing failures that could adversely impact the product's designed operation.
In built-in self-test (BIST) logic, hardware and/or software are built into ICs allowing them to test their own operation, as opposed to reliance on external automated test equipment (ATE). Generally, this additional hardware comprises a pseudo-random pattern generator (PRPG), implemented by a linear feedback shift register, and a test response analyzer, typically, a multiple input shift register (MISR). With BIST logic, pseudo random test patterns are applied to the chip under test (CUT) through scan chains using the PRPG, and the response of the CUT to these pseudo-random patterns is compacted into a test signature by the test response analyzer. Since BIST logic only applies pseudo-random patterns, it cannot achieve the same fault coverage as a scan-based structural test set generated by an Automatic Test Pattern Generation (ATPG) tool, which requires an extremely large test data volume. However, since BIST logic uses an on-chip PRPG, it requires minimal support from the external test environment. Ordinarily, the only interaction with the outside test environment is at the beginning of testing when an initial seed for the PRPG along with a start signal is provided, and at the end of testing when the test signature in the test response analyzer is compared with a “golden”, i.e., good, signature. For this reason, BIST logic can be used to apply millions of test patterns to the CUT with the aim of capturing an unexpected response. The main advantage of BIST logic is the ability to test internal circuits having no direct connections to external pins. Another advantage is the ability to initiate the BIST logic of a CUT while running the built-in self-test or a power-on self-test of the manufactured IC.
OPMISR testing, like BIST logic, uses the MISR to collect compressed results, thus saving tester data volume, but rather than using PRPG generated test data, like Automatic Test Pattern Generation (ATPG) testing it uses deterministic data stored on the tester. In this manner the data volume is greater than that of BIST logic, but much reduced from normal full scan ATPG patterns. The data can also be more focused on the needs for the specific design so will get better test coverage than the pseudo-random BIST logic design.
BIST and OPMISR logic design and test methodology support level sensitive scan design (LSSD) or generalized scan design (GSD, also known as MUXscan), to facilitate circuit testing and diagnostics. LSSD or GSD modify existing sequential elements, e.g., flip-flops, in the IC design to support serial shift capability, in addition to their normal operation. In effect, these modified elements are connected into serial chains to make long shift registers. Each scan chain element operates as both a primary input or a primary output during test, enhancing the controllability and observability of internal nodes of the IC design. However, only an external ATPG tool having the required tester data volume can carry out application of logic test patterns to be applied to a fully isolated combinatorial block, i.e., a full scan.
DFT compression schemes using multiple input shift registers (MISRs) are efficient for go/no go testing and mitigate test data volume problems, but the consequent compression makes failure diagnosis simulation difficult or even impossible. In addition, the compression can alias the MISR observe or signature fail data, significantly impacting diagnostic resolution or not converging to a solution. Thus, failure diagnosis is substantially degraded, which negatively impacts volume diagnostics for IC yield learning. Furthermore, for IC designs with high logic content, the majority of logic test patterns are compressed tests, which means that if they fail, there is no diagnostic alternative on the tester to collect full-scan diagnostics fail data, which could isolate the location of a single latch that is observed to fail.
There remains a need for efficient diagnostics from signatures of a multiple input shift register (MISR) in built-in self-test (BIST) logic, including On-product MISR (OPMISR) logic, to isolate one or more latches that observe fail during a compressed test pattern.